Some types of integrated power MOS transistors have an n-doped buried layer contacted by a highly n-doped sinker. An n-doped sinker confined within the interior of a trench and isolated laterally by a thin oxide layer reduces cell spacing compared to sinkers formed by diffusion. The same integrated power MOS transistors typically have a p-doped sinker or substrate contact at the periphery and between two neighbouring power MOS transistors to electrically isolate the transistors from each other. The substrate contact is also conventionally confined within a trench and isolated laterally by insulated sidewalls. However, the mesa of semiconductor material between the sinkers is floating. As such, both p-type and n-type channels can form in theses regions. The insulated sidewalls must be thick enough to block the maximum voltage of these parasitic devices. For example, an oxide thickness of 700 nm is typically used to ensure suitable voltage protection. Subsequent processing for opening the oxide at the bottom of the trenches leads to considerable thinning of the sidewall oxide to about 450 nm at the upper part of the trenches. Higher blocking voltages require even thicker oxides which cause stress that can result in crystal defects. A trench structure that allows higher blocking voltage with the same oxide thickness during processing would be beneficial.
The floating mesa of semiconductor material between neighbouring n-type and p-type sinkers also causes parasitic capacitances between the n-type and p-type sinkers which are much higher than capacitances between widely spaced diffused sinkers due to the formation of inversion and accumulation channels. Furthermore, the n-type and p-type sinker termination regions of a conventional power transistor array tend to consume about 2×3 μm per trench and require 6 μm spacing. Processing constraints often require the n-type and p-type sinker trenches to be closed rings. Space and thereby cost can be saved by reducing the number of rings.